A. Technical Field
Fabrication of small dimensioned circuit and circuit elements--e.g., large scale integrated silicon circuits (silicon LSI), involves one or more pattern delineation steps in which continuous layered material is removed by etching. Pattern configuration is generally determined by an overlying layer of aperture-patterned resist material. In accordance with prevalent practice at this time, resist patterns result from (1) exposure through a discrete mask, (2) followed by development to (a) remove unexposed material (negative resist) or (b) remove exposed material (positive resist).
The trend toward miniaturization increases the difficulty with which successive mask patterns may be superimposed. It is generally expected that further reduction to design rules in the micron or submicron range will result in increasing acceptance of maskless procedures (direct processing) in accordance with which pattern delineation is initially carried out directly in resist layers on the device undergoing fabrication.
The trend toward smaller structures is having profound effects on device fabrication, itself. Wet etching, in general use for years, and still generally satisfactory at the 4 micron level, is yielding to dry processing. Dry etching procedures, exemplified by plasma etching, offer promise of improved resolution, for example by lessening of line shrinkage inter alia, due to undercutting. Other advantages of dry etching include less severe resist adherence requirements and relative ease of disposal of etchant biproducts.
Plasma etching has been satisfactorily applied to the materials normally encountered in the fabrication of silicon integrated circuits (SIC). A structure now being manufactured includes successive layers of plasma deposited silicon nitride, aluminum, phosphorous doped amorphous oxide ("p glass"), polycrystalline silicon ("polysilicon"), field and gate layers of thermally produced silicon oxide, a transitory layer of pyrolytic silicon nitride, and, finally, the silicon wafer, itself. Plasma etching of SICs and other integrated circuits may also involve boron nitride. Plasma etching--sometimes called plasma stripping--is used in the removal of each resist layer after its masking function has been served. Resist removal may take on a somewhat more critical aspect during "lift off" procedures. Integrated circuitry, as well as discrete devices, involving other technologies as well as silicon, may depend on dry processing for these reasons. Materials to be encountered may include soft magnetic, as well as remanent magnetic, materials (e.g., permalloy and substituted yttrium iron garnet), as active optical materials (e.g., lithium niobate, lithium tantalate) as well as other metals and intermetallic compounds.
B. History
Perhaps the earliest used and still the most prevalent plasma etching procedure is based on the well-known CF.sub.4 -O.sub.2 etchant. This material, long commercially available, has been applied to many of the above-listed materials and others in a variety of reactor designs. CCl.sub.4 -based etchants are usefully applied to many of the above materials.
Simultaneous etching of a plurality of wafers with CF.sub.4 -O.sub.2 etchant may be complicated by the well-known "loading effect" phenomenon. Use of CCl.sub.4 is generally characterized by this effect on all materials to which it is commonly applied. Dependence of etch rate on surface area to be etched, may result in unacceptably low throughput for high loading. This effect, in itself a significant problem, is further complicated by uneven etching. Non-uniformity, inter or intra-wafer, sometimes tolerable may become serious depending on such factors as (a) etch ratio for material to be etched relative to underlying substrate, (b) the sometimes related factor of need for and type of end point detection, (c) feature size tolerance (a consequence of loading is a sudden uncontrollable increase in etch rate as clearing begins, leading to uncontrolled undercutting during a required period of overetching).
Attempts to alleviate the loading effect through improved reactor design have been ineffective. Improvement in reactor design has, however, had some beneficial effect on etch uniformity, although non-uniformity is inherent to loading and continues to be a problem for fine-dimensioned circuitry. See R. G. Poulsen, J. Vac. Sci. Technol., 14, 266 (1977) for a description of reactors presently in use.
It is evident from the literature that the loading effect is well known. It is also known that, while it is a significant obstacle for some materials, it is not for others. So for example, use of CF.sub.4 -O.sub.2, complicated by loading when applied to polysilicon etching, is unencumbered by loading as applied to silicon oxide. Substitution of other etchants for SiO.sub.2 etching has not changed the situation. Loading does not appear to be a problem for this material.